(a) Field of the Invention
The present invention relates to a method for forming an interconnect pattern in a semiconductor device and, more particularly, to a method suitable for forming a fine interconnect pattern having less short-circuit failure.
(b) Description of the Related Art
In a process for forming an interconnect structure in a semiconductor device, an Alxe2x80x94Cu alloy is generally used for the interconnect pattern. In a typical example, Alxe2x80x94Cu alloy includes 99.5% Al and 0.5% Cu at a weight ratio.
FIGS. 1A to 1E show consecutive steps of a conventional process for forming an interconnect pattern having the Alxe2x80x94Cu alloy. In FIG. 1A, on an underlying insulator layer 12 such as a SiO2 film, a Ti/TiN film 14 including a Ti layer and a TiN layer is deposited as an adhesion/barrier layer by using a sputtering technique etc, followed by depositing an Alxe2x80x94Cu alloy layer 16 thereon by using a sputtering technique etc.
Subsequently, as shown in FIG. 1B. a TiN/Ti film 18 is deposited on the Alxe2x80x94Cu alloy layer 16 by a sputtering technique etc., thereby obtaining a combination interconnect layer 20 including the Ti/TiN film 14, the Alxe2x80x94Cu alloy layer 16 and the TiN/Ti film 18.
Thereafter, as shown in FIG. 1C, the Ti/TiN film 18 is subjected to an O2-plasma treatment as a pretreatment for patterning the combination interconnect layer 20.
Subsequently, as shown in FIG. 1D, a photoresist mask 22 having a design interconnect pattern is formed on the TiN/Ti film 18, followed by patterning the combination interconnect layer 20 by using a plasma-enhanced etching technique using the photoresist mask 22 as an etching mask. Thus, an interconnect pattern 24 is obtained which includes the Ti/TiN film 14, the Alxe2x80x94Cu alloy layer 16 and the TiN/Ti film 18 consecutively formed on the underlying insulator layer 12.
In the conventional technique as described above, the possibility of a short-circuit failure occurring in the interconnect pattern increases together with the development of a finer design rule and higher integration in the semiconductor device, both of which involve a smaller line gap in the interconnect pattern.
The short-circuit failure degrades the product yield of the semiconductor devices, and thus a method for forming the interconnect pattern free from such a failure has long been desired.
In view of the above problem in the conventional technique, it is an object of the present invention to provide a method for forming a fine interconnect pattern in a semiconductor device, which is capable of forming an interconnect pattern having less short-circuit failure.
The present invention provides a method for forming an interconnect pattern including the consecutive steps of: depositing an interconnect film including at least an Alxe2x80x94Cu alloy layer on an underlying layer; plasma treating the interconnect film; heat-treating the interconnect film at a temperature between 280xc2x0 C. and 400xc2x0 C.; and patterning the interconnect film by using an etching mask to form the interconnect pattern.
The heat treating of the interconnect film at the specified temperature after the plasma treatment, such as an O2-plasma or Ar-plasma treatment, re-distributes the Cu particles which occur within the Alxe2x80x94Cu alloy layer during the plasma treatment, thereby suppressing the short-circuit failure caused by the Cu particles in the resultant interconnect pattern.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.